We have different low power design techniques available at the front-end and at the back-end of VLSI design flow to reduce the design's dynamic and static power. Some of the methods are clock gating, power gating, lowering supply voltage and frequency.
At lower nodes, many other techniques have been investigated and used in designs. Below we will discuss some basic and yet important techniques that are frequently used at the back-end level of VLSI design flow.
a) Reduction in switching activity: There are many ways for reducing switching activity. We have an age-old and conventional technique known as clock gating. It is quite simple in which we block the clock signals of any block whenever the data inside the block is not changing or when the block is not required.
In the above-given figure, the Block A clock is dependent upon enable signal. Whenever the signal becomes high, it provides a clock to block A. Here we have used AND gate as a clock gating cell, but there will chances of glitches in the clock, which will be propagated to the block and inturns to functionality errors. To avoid this case, we use ICG cells (Integrated clock gating cells) available in. lib provided by the foundry based on the latch to avoid eliminate any glitch on enable signal which can be propagated through the clock.
Another technique that can help us to reduce dynamic power by lowering switching activity is replacing binary counters with a gray counter. For example: In asynchronous FIFO, we can use a gray counter instead of a binary counter to synchronize read and write pointers.
b) By reducing supply voltage: We know that the square of supply voltage is directly proportional to dynamic power. By lowering a supply voltage, we can reduce dynamic power dissipation in design. But it can impact the speed and performance of design and may give rise to subthreshold leakage currents.
c) Multi-VT Design: If two different cell libraries of HVT and LVT are available, we can replace some parts of the design with HVT and LVT. For example, The high-performance block is synthesized by HVT cells, and the timing critical block can be synthesized by LVT cells.
d) Multi-voltage Design: The same IC can have blocks working on different voltages according to their performance requirements. For example, a SOC has a core and different peripherals like UART, SPI, etc., which can perform DSP algorithms. In this case, to perform such heavy processing, we need high performance from the core. We have to operate it with a high power supply, and other peripherals can operate at a lower voltage. A level shifter is used, which will shift from one voltage domain to another. Similarly, the signals leaving from one domain to another should be shifted using level shifters.
In the above figure, the level shifter is connected with both voltage supplies and shifting the signal levels from low voltage domain to high voltage domain.
e) Power Gating: It is a technique in which we can turn off the power supply or a part of IC by using a power gating cell. Thus it can help in reducing the dynamic as well as static power of the design. This technique can be implemented using a power controller, power network, isolation cells, and retention register. A power controller is a logic block that will signal a specific block to turn on or turn off the power supply.
The power gating cell is implemented using an HVT transistor from MTCMOS (multi-threshold CMOS) technology to minimize leakage currents and static power.
In the above figure, we have a switch connected in between VDD and block is known as a header switch, and if a switch is connected in between the block and VSS, it is known as a Footer switch. This is strategy is also known as a coarse-grain strategy as power gating is directly implemented over a block.
a) Drain header and power footer gating. b)Drain footer and power header gating
In the above-given figure, we have some advanced power gating and drain gating techniques. This is strategy is also known as a fine-grain strategy.
Fig. Isolation cells with an always-on block and power down block
Retention register: The data residing inside the power down the block can be saved by storing the data inside the retention register in power-down mode. Whenever the block is powered up, the same data can be restored from retention registers. The retention register should always be powered up.
f) Dynamic voltage and frequency scaling: It is the technique where we change the frequency and voltage of the designs according to workload upon them; if low performance is required, we can use low voltage and low frequency. For high performance, the same block should be connected to higher voltage levels. To achieve this, we need to provide different voltage levels inside the chip to switch in between them whenever it's required. We can extend this by using power gating to shut down the specific block when it is not in use.
In the next article, we will discuss UPF and how we can specify the information related to supply network, isolation cells, retention registers, etc., in our design for power management.
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References:
1. https://lmr.fi/int/multi-voltage-design-power-management/
2. Panwar, Shikha & Piske, Mayuresh & Madgula, Aatreya. (2014). Performance Analysis of Modified Drain Gating Techniques for Low Power and High-Speed Arithmetic Circuits. VLSI Design. 2014. 1-5. 10.1155/2014/380362.
3. T. Hattori, "Design
methodology of low-power microprocessors," Proceedings of the ASP-DAC
Asia and South Pacific Design Automation Conference, 2003., Kitakyushu, Japan,
2003, pp. 390-393, DOI: 10.1109/ASPDAC.2003.1195046
4. https://semiengineering.com/knowledge_centers/low-power/techniques/power-isolation/
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