Power consumption in ASIC.

In older designs, we were worried about timing and area to save the cost of the design but now the power is becoming crucial day by day due to development in the manufacturing unit and leading to the scaling of technologies from µm to nm and impacted the density of transistors to increase in the same area causing more power consumption and has become a worrisome topic. Increased power consumption in design leads to an added cost of manufacturing the IC due to the usage of ceramic packaging of IC, modified heat sinks, and the cooling mechanism that will be needed to save IC from malfunctioning.

Companies are investing a lot of money and resources in R&D to solve this issue. Each company has a specific PPA team that works on trade-offs between power, performance, and area.

Power consumption is broadly divided into two types,

 1. Dynamic power: This type of power consumption is due to switching activity in design and internal power consumption. Switching power involves charging and discharging of the external capacitances in design running on Vdd and frequency.

P(Dynamic) = (Vdd)^2*C*F 

Vdd: Power supply, C: Load capacitance, F: Frequency. 

Internal power consumption occurs for a very short duration of time due to a short circuit current, in which our PMOS and NMOS are directly connected to each other and form a conducting path between Vdd and ground. For example in an inverter as per DC characteristic, there is a point in VTC curve at which vin=vout which is also known as switching threshold in which pmos and nmos are in a saturation region.

2. Leakage Power: Leakage power was negligible in older technologies but at deep submicron technologies it has been increased, sometimes it is even comparable to the dynamic power consumption of the design. The subthreshold current, gate current and reverse bias PN junction current contribute to the leakage power. We will discuss each of them one by one:

a) Subthreshold current: Due to scaling, we have reduced gate threshold voltage of mosfet's because of which MOSFET can conduct in small amount even when the gate voltage is less than the threshold voltage and current can flow from drain to source which is also known as sub-threshold current and contributes to power leakage.

b) Reverse bias PN junction current:  From the basics of the PN junction, we know it can conduct current in forward bias condition, but in reverse bias junction due to large depletion width it can't conduct any current. But there is a small amount of current which flows in reverse bias condition due to the minority charge carrier which is known as reverse saturation current. The same current flows here in the PN junction formed by drain and body/substrate in reverse bias condition. 

c) Gate leakage current: It is because of the thin oxide layer, which is too small and has only a few layers of oxide atoms because of which tunnelling effect can occur and current can flow from gate to source or drain.

The power leakage occurs mainly in an idle. But it can be reduced to a greater extent by using HVT cells and lowering voltage supply or by turning off design when not in use by using power and sleep cells.

We will discuss different types of techniques that can be used and how we can implement them in design in the next article.

Thank you for reading this article.

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